1. Field of the Invention
The present invention relates to a tape automated bonding (TAB) tape for a semiconductor package such as a tape carrier package (TCP) and a chip on film (COF) and more particularly to test pad layout of the TAB tape.
2. Description of the Related Art
Tape automated bonding (TAB) was introduced as a replacement for a conventional wire bonding technology. TAB is now used for liquid crystal displays, watches, cameras, memory cards, calculators, personal computers and other electronic devices. TAB provides a high-density interconnect from IC chips to substrate, allowing full automation of the bonding of one end of the tape wiring pattern to the IC chips and the other end of the tape wiring pattern to the substrate.
FIG. 1 shows a conventional TAB tape 10. A wiring pattern 30 is formed on a base film 20. The base film 20 has a window 24, typically formed near the center, through which the semiconductor IC chip is connected to the wiring pattern 30 by inner lead bonding (ILB). Sprocket holes 26 are formed on each edge of the base film 20 at regular intervals. The wiring pattern 30 also typically includes input terminal patterns 32 extending in one direction from the window 24 and output terminal patterns 34 extending in the opposite direction from the window 24. Test pads 36 and 38 are provided at the ends of the input/output terminal patterns 32 and 34, respectively. The input terminal patterns 32 and output terminal patterns 34 are generally parallel to the rows of sprocket holes 26. For clarity, the test pads 36 formed at the ends of the input terminal patterns 32 are hereinafter described as input test pads. Likewise, the test pads 38 formed at the ends of the output terminal patterns 34 are hereinafter described as output test pads.
The TAB tape 10 comprises a package area P1 substantially comprising that portion of the tape that will be included in the final packaged product, input test pad area IT1 and output test pad area OT1 formed at opposite ends of the package area P1 and a cutting area C1 for separating the package area P1 from the output test pad area OT1. The input test pad area IT1 contains the input test pads 36 and an output test pad area OT1 contains the test pads 38. Depending on the particular TAB tape configuration other cutting areas (not illustrated) may be provided for separating the package area P1 from other portions of the TAB tape such as the edge portions containing the sprocket holes 26 and the input test pad area IT1.
Referring to FIG. 2, each of the output terminal patterns 34 connects to a corresponding test pad. The output test pads 38 are arranged a series of groups 40 arranged across the tape 10 at regular intervals. FIG. 2 illustrates the layout of six output test pads 38a-38f that form one group 40. As illustrated, the output test pads 38a-38f are arranged in six rows, with a single output test pad in each row corresponding to a single line of the output terminal pattern.
Although the conventional TAB tape 10 may provide certain advantages for easily manufacturing test devices, the output test pad area OT1 occupies a large portion of the base film 20. The area consumed by the output test pad area OT1 reduces the number of semiconductor packages that may be formed from a length of TAB tape and increases the overall cost of the package.